1. Field of the Invention
The present invention relates to a semiconductor memory device and, more particularly, to a semiconductor memory device in which memory cells are refreshed.
2. Description of the Background Art
With a recent rapid advance of semiconductor integrated technology, a dynamic RAM (hereinafter referred to as a DRAM) tends to have a larger capacity. The larger the capacity becomes, the more the number of word lines included in a DRAM increases.
Since a DRAM can not store information in each memory cell in a nonvolatile manner, it is necessary to refresh information stored in each memory cell periodically to prevent destruction of information. A cycle number necessary to refresh the whole memory cell array (hereinafter referred to as a refresh cycle number) is fixed separately according to a capacity of a DRAM. For example, a DRAM of 1M bit is fixed to have a refresh cycle number of 512 cycle/8 ms (hereinafter such a refresh operation is referred to as a 512 refresh). A DRAM of 4M bit is fixed to have a refresh cycle number of 1024 cycle/16.4 ms (hereinafter such a refresh operation is referred to as a 1024 refresh).
FIG. 11 is a schematic diagram for describing a refresh operation in a DRAM of 1M bit. Referring to the figure, a memory cell array MCA is divided into, for example, two blocks BK1 and BK2 in order to carry out a 512 refresh. First block BK1 and second block BK2 each include 512 word lines WL. A row decoder is divided into two parts corresponding to first block BK1 and second block BK2. Two row decoders RD each select one word line WL. Therefore, as a whole memory cell array MCA, two word lines WL are selected simultaneously. By selection of word lines WL, a plurality of memory cells connected thereto are refreshed simultaneously. A refresh operation of the whole memory cell array MCA is completed by repeating a selecting operation of a word line WL by each row decoder RD 512 times. That is, the 512 refresh operation can be carried out in a DRAM of 1M bit.
FIG. 12 is a schematic diagram for showing a refresh operation in a DRAM of 4M bit. Referring to the figure, a memory cell array MCA is divided into, for example, four blocks BK1-BK4 in order to implement a 1024 refresh. Each block includes 1024 word lines. A row decoder is divided into four to correspond to four blocks BK1-BK4 of memory cell array MCA. Each row decoder RD selects one word line WL in a refresh mode. Therefore, as a whole memory cell array MCA, four word lines WL are selected simultaneously. As in a DRAM of 1M bit, a plurality of memory cells connected to the selected word lines are refreshed simultaneously. A refresh operation of the whole memory cell array MCA is completed by repeating selection of word lines 1024 times. That is, a 1024 refresh operation can be carried out in a DRAM of 4M bit.
A demand for using a DRAM of a large capacity frequently arises among users who desire to improve a system using a DRAM. However, if a DRAM included in a system is replaced with one with a large capacity, a refresh cycle number of a DRAM changes, and a structure and/or a program of the system should be modified accordingly. Since such modification is extremely troublesome and costs time and money, users desire to use a DRAM having the same refresh cycle number as much as possible. In order to satisfy such a demand, it is proposed to combine a plurality of DRAMs of a small capacity to provide a large capacity. However, in such a method, a problem arises that an area required for DRAM increases and so does power consumption. Another problem also exists that it costs more to use a combination of a plurality of DRAMs of a small capacity than to use one DRAM of a large capacity.
One possible solution of the above problems offered by manufactures is to produce several kinds of products having different refresh cycle numbers for DRAMS of the same capacity. However, such a production in a small quantity with many varieties raises the cost of product, and therefore prevents reduction of cost which can be achieved by mass production. Even though a variety of products are produced in a master slice approach in which design modification is relatively easy, production efficiency is low and the cost increases compared to mass production of the same kind of product.
As described above, since a conventional DRAM has one fixed refresh cycle number for each capacity, it is difficult to change a DRAM which has been in use with a DRAM having different capacities.